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1. general description the pca9541 is a 2-to-1 i 2 c-bus master selector designed for high reliability dual master i 2 c-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. the two masters (for example, primary and back-up) are located on separate i 2 c-buses that connect to the same downstream i 2 c-bus slave devices. i 2 c-bus commands are sent by either i 2 c-bus master and are used to select one master at a time. either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. the failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream i 2 c-bus. two versions are offered for different architectures. pca9541/01 with channel 0 selected at start-up and pca9541/03 with no channel selected after start-up. the interrupt outputs are used to provide an indication of which master has control of the bus. one interrupt input ( int_in) collects downstream information and propagates it to the 2 upstream i 2 c-buses ( int0 and int1) if enabled. int0 and int1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. those interrupts can be disabled and will not generate an interrupt if the masking option is set. a bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a stop condition in order to set the downstream i 2 c-bus devices to an initialized state before actually switching the channel to the selected master. an interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. an internal bus sensor senses the downstream i 2 c-bus traf?c and generates an interrupt if a channel switch occurs during a non-idle bus condition. this function is enabled when the pca9541 recovery/initialization is not used. the interrupt signal informs the master that an external i 2 c-bus recovery/initialization needs to be performed. it can be disabled and an interrupt will not be generated. the pass gates of the switches are constructed such that the v dd pin can be used to limit the maximum high voltage, which will be passed by the pca9541. this allows the use of different bus voltages on each pair, so that 1.8 v, 2.5 v, or 3.3 v devices can communicate with 5 v devices without any additional protection. the pca9541 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. external pull-up resistors pull the bus to the desired voltage level for each channel. all i/o pins are 6.0 v tolerant. pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset rev. 07 2 july 2009 product data sheet
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 2 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset an active low reset input allows the pca9541 to be initialized. pulling the reset pin low resets the i 2 c-bus state machine and con?gures the device to its default state as does the internal power-on reset (por) function. 2. features n 2-to-1 bidirectional master selector n i 2 c-bus interface logic; compatible with smbus standards n pca9541/01 powers up with channel 0 selected n pca9541/03 powers up with no channel selected and either master can take control of the bus n active low interrupt input n 2 active low interrupt outputs n active low reset input n 4 address pins allowing up to 16 devices on the i 2 c-bus n channel selection via i 2 c-bus n bus initialization/recovery function n bus traf?c sensor n low r on switches n allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses n no glitch on power-up n supports hot insertion n software identical for both masters n low standby current n operating power supply voltage range of 2.3 v to 5.5 v n 6.0 v tolerant inputs n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so16, tssop16, hvqfn16 3. applications n high reliability systems with dual masters n gatekeeper multiplexer on long single bus n bus initialization/recovery for slave devices without hardware reset n allows masters without arbitration logic to share resources
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 3 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 4. ordering information 5. marking table 1. ordering information t amb = - 40 c to +85 c type number package name description version pca9541d/01 so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 pca9541pw/01 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pca9541bs/01 hvqfn16 plastic thermal enhanced very thin quad ?at package; no leads; 16 terminals; body 4 4 0.85 mm sot629-1 pca9541d/03 so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 pca9541pw/03 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pca9541bs/03 hvqfn16 plastic thermal enhanced very thin quad ?at package; no leads; 16 terminals; body 4 4 0.85 mm sot629-1 table 2. marking codes type number topside mark pca9541d/01 pca9541d/01 pca9541pw/01 9541/01 pca9541bs/01 41/1 pca9541d/03 pca9541d/03 pca9541pw/03 9541/03 pca9541bs/03 41/3
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 4 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 6. block diagram fig 1. block diagram of pca9541 pca9541 002aab382 input filter scl_mst0 sda_mst0 stop detection a3 a2 a1 a0 power-on reset i 2 c-bus control and register bank reset v dd input filter scl_mst1 sda_mst1 stop detection bus sensor slave channel switch control logic scl_slave sda_slave bus recovery/ initialization oscillator interrupt logic v ss int0 int1 int_in
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 5 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 7. pinning information 7.1 pinning fig 2. pin con?guration for so16 fig 3. pin con?guration for tssop16 fig 4. pin con?guration for hvqfn16 pca9541d/01 pca9541d/03 int0 v dd sda_mst0 int_in scl_mst0 sda_slave reset scl_slave scl_mst1 a3 sda_mst1 a2 int1 a1 v ss a0 002aab379 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 int0 sda_mst0 scl_mst0 reset scl_mst1 sda_mst1 int1 v ss pca9541pw/01 pca9541pw/03 002aab380 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 v dd int_in sda_slave scl_slave a3 a2 a1 a0 v ss 002aab381 pca9541bs/01 pca9541bs/03 transparent top view sda_mst1 a2 scl_mst1 a3 reset scl_slave scl_mst0 sda_slave int1 a0 a1 sda_mst0 int0 v dd int_in 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 6 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 7.2 pin description [1] hvqfn16 package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. table 3. pin description symbol pin description so16, tssop16 hvqfn16 int0 1 15 active low interrupt output 0 (external pull-up required) sda_mst0 2 16 serial data master 0 (external pull-up required) scl_mst0 3 1 serial clock master 0 (external pull-up required) reset 4 2 active low reset input (external pull-up required) scl_mst1 5 3 serial clock master 1 (external pull-up required) sda_mst1 6 4 serial data master 1 (external pull-up required) int1 7 5 active low interrupt output 1 (external pull-up required) v ss 86 [1] supply ground a0 9 7 address input 0 (externally held to v ss or v dd ) a1 10 8 address input 1 (externally held to v ss or v dd ) a2 11 9 address input 2 (externally held to v ss or v dd ) a3 12 10 address input 3 (externally held to v ss or v dd ) scl_slave 13 11 serial clock slave (external pull-up required) sda_slave 14 12 serial data slave (external pull-up required) int_in 15 13 active low interrupt input (external pull-up required) v dd 16 14 supply voltage
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 7 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 8. functional description refer to figure 1 bloc k diag r am of pca9541 . 8.1 device address following a start condition, the upstream master that wants to control the i 2 c-bus or make a status check must send the address of the slave it is accessing. the slave address of the pca9541 is shown in figure 5 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed. when set to logic 1 a read is selected, while logic 0 selects a write operation. remark: reserved i 2 c-bus addresses must be used with caution since they can interfere with: ? reserved for future use i 2 c-bus addresses (1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) 8.2 command code following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9541, which will be stored in the command code register. the 2 lsbs are used as a pointer to determine which register will be accessed. if the auto-increment ?ag is set (ai = 1), the two least signi?cant bits of the command code are automatically incremented after a byte has been read or written. this allows the user to program the registers sequentially or to read them sequentially. ? during a read operation, the contents of these bits will roll over to 00b after the last allowed register is accessed (10b). fig 5. slave address 002aab390 1 1 1 a3 a2 a1 a0 r/w fixed hardware selectable fig 6. command code 002aab391 0 0 0 ai 0 0 b1 b0 register number auto-increment
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 8 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset ? during a write operation, the pca9541 will acknowledge bytes sent to the ie and control registers, but will not acknowledge a byte sent to the interrupt status register since it is a read-only register. the 2 lsbs of the command code do not roll over to 00b but stay at 10b. only the 2 least signi?cant bits are affected by the ai ?ag. unused bits must be programmed with zeros. any command code (write operation) different from 000ai 0000, 000ai 0001, and 000ai 0010 will not be acknowledged. at power-up, this register defaults to all zeros. each system master controls its own set of registers, however they can also read speci?c bits from the other system master. 8.3 interrupt enable and control registers description when a master seeks control of the bus by connecting its i 2 c-bus channel to the pca9541 downstream channel, it has to write to the control register (reg#01). bits mybus and buson allow the master to take control of the bus. the mybus and the nmybus bits determine which master has control of the bus. t ab le 9 explains which master gets control of the bus and how. there is no arbitration. any master can take control of the bus when it wants regardless of whether the other master is using it or not. the buson and the nbuson bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. t ab le 10 explains when the upstream bus is connected or disconnected. internally, the state machine does the following: ? if the combination of the buson and the nbuson bits causes the upstream to be disconnected from the downstream bus, then that is done. so in this case, the values of the mybus and the nmybus do not matter. table 4. command code register b1 b0 register name type register function 0 0 ie r/w interrupt enable 0 1 control r/w control switch 1 0 istat r only interrupt status 1 1 not allowed fig 7. internal register map 002aab392 ie 0 control 0 istat 0 ie 1 control 1 istat 1 pca9541 reg#00 reg#01 reg#10 ie control istat master 0 scl_mst0 sda_mst0 reg#00 reg#01 reg#10 ie control istat master 1 scl_mst1 sda_mst1
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 9 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset ? if a master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that it is no longer connected to the downstream bus. this is indicated by setting the buslost bit in the interrupt status register. ? if the combination of the buson and the nbuson bits causes a master to be connected to the downstream bus and if there is no change in the buson bits since when the disconnect took effect, then the master requesting the bus is connected to the downstream bus. if it requests a bus initialization sequence, then it is performed. ? if there is no change in the combination of the buson and the nbuson bits and a new master wants the bus, then the downstream bus is disconnected from the old master that was using it and the new master gets control of it. again, the bus initialization if requested is done. the appropriate interrupt signals are generated. after a master has sent the bus control request: 1. the previous master is disconnected from the i 2 c-bus. an interrupt to the previous master is sent through its int line to let it know that it lost control of the bus. buslost bit in the interrupt status register is set. this interrupt can be masked by setting the buslostmsk bit to logic 1. 2. a built-in bus initialization/recovery function can take temporary control of the downstream channel to initialize the bus before making the actual switch to the new bus master. this function is activated by setting the businit to logic 1 by the master during the same write sequence as the one programming mybus and buson bits. when activated and whether the bus was previously idle or not: a. 9 clock pulses are sent on the scl_slave. b. sda_slave line is released (high) when the clock pulses are sent to scl_slave. this is equivalent to sending 8 data bits and a not acknowledge. c. finally a stop condition is sent to the downstream slave channel. this sequence will complete any read transaction which was previously in process and the downstream slave con?gured as a slave-transmitter should release the sda line because the pca9541 did not acknowledge the last byte. 3. when the initialization has been requested and completed, the pca9541 sends an interrupt to the new master through its int line and connects the new master to the downstream channel. businit bit in the interrupt status register is set. the switch operation occurs after the master asking the bus control has sent a stop command. this interrupt can be masked by setting the businitmsk bit to logic 1. 4. when the bus initialization/recovery function has not been requested (businit = 0), the pca9541 connects the new master to the slave downstream channel. the switch operation occurs after the master asking the bus control has sent a stop command. pca9541 sends an interrupt to the new master through its int line if the built-in bus sensor function detects a non-idle condition in the downstream slave channel at the switching time. busok bit in the interrupt status register is set. this means that a stop condition has not been detected in the previous bus communication and that an external bus recovery/initialization must be performed. if an idle condition has been detected at the switching time, no interrupt will be sent. this interrupt can be masked by setting the busokmsk bit to logic 1. interrupt status can be read. see section 8.4 interr upt status registers for more information.
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 10 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset the mytest and the nmytest bits cause the interrupt pins of the respective masters to be activated for a functional interrupt test. remark: the regular way to proceed is that a master asks to take the control of the bus by programming mybus and buson bits based on nmuybus and nbuson values. nevertheless, the same master can also decide to give up the control of the bus and give it to the other master. this is also done by programming the mybus and buson bits based on nmybus and nbuson values. remark: any writes either to the interrupt enable register or the control register cause the respective register to be updated on the 9th clock cycle, that is, on the rising edge of the acknowledge clock cycle. remark: the actual switch from one channel to another or the switching off of both the channels happens on a stop command that is sent by the master requesting the switch. 8.3.1 register 0: interrupt enable (ie) register (b1:b0 = 00b) this register allows a master to read and/or write (if needed) mask options for its own channel. the interrupt enable register described below is identical for both the masters. nevertheless, there are physically 2 internal interrupt enable registers, one for each upstream channel. when master 0 reads/writes in this register, the internal interrupt enable register 0 will be accessed. when master 1 reads/writes in this register, the internal interrupt enable register 1 will be accessed. table 5. register 0 - interrupt enable (ie) register (b1:b0 = 00b) bit allocation 7 6 5 4 3 2 1 0 0000b uslostmsk busokmsk businitmsk intinmsk table 6. register 0 - interrupt enable (ie) register bit description legend: * default value bit symbol access value [1] description 7:4 - r only 0* not used 3 buslostmsk r/w 0* an interrupt on int will be generated after the other master has been disconnected. 1 an interrupt on int will not be generated after the other master has been disconnected. 2 busokmsk r/w 0* after connection is requested and bus initialization not requested (businit = 0), an interrupt on int will be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment. remark: channel switching is done automatically after the stop command. 1 after connection is requested and bus initialization not requested (businit = 0), an interrupt on int will not be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). remark: channel switching is done automatically after the stop command.
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 11 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [1] default values are the same for pca9541/01 and pca9541/03. 8.3.2 register 1: control register (b1:b0 = 01b) the control register described below is identical for both the masters. nevertheless, there are physically 2 internal control registers, one for each upstream channel. when master 0 reads/writes in this register, the internal control register 0 will be accessed. when master 1 reads/writes in this register, the internal control register 1 will be accessed. [1] default values are the same for pca9541/01 and pca9541/03. 1 businitmsk r/w 0* after connection is requested and bus initialization requested (businit = 1), an interrupt on int will be generated when the bus initialization is done. remark: channel switching is done after bus initialization completed. 1 after connection is requested and bus initialization requested (businit = 1), an interrupt on int will not be generated when the bus initialization is done (masked). remark: channel switching is done after bus initialization completed. 0 intinmsk r/w 0* interrupt on int_in will generate an interrupt on int. 1 interrupt on int_in will not generate an interrupt on int (masked) table 6. register 0 - interrupt enable (ie) register bit description continued legend: * default value bit symbol access value [1] description table 7. register 1 - control register (b1:b0 = 01b) bit allocation 7 6 5 4 3 2 1 0 nteston teston 0 businit nbuson buson nmybus mybus table 8. register 1 - control register (b1:b0 = 01b) bit description legend: * default value bit symbol access value [1] description 7 nteston r/w 0* a logic level high to the int line of the other channel is sent (interrupt cleared). 1 a logic level low to the int line of the other channel is sent (interrupt generated). 6 teston r/w 0* a logic level high to the int line is sent (interrupt cleared). 1 a logic level low to the int line is sent (interrupt generated). 5 - r only 0* not used 4 businit r/w 0* bus initialization is not requested. 1 bus initialization is requested. 3 nbuson r only see t ab le 11 nbuson bit along with buson bit decides whether any upstream channel is connected to the downstream channel or not. see t ab le 10 , t ab le 11 , and t ab le 12 . 2 buson r/w see t ab le 11 buson bit along with the nbuson bit decides whether any upstream channel is connected to the downstream channel or not. see t ab le 10 , t ab le 11 , and t ab le 12 . 1 nmybus r only see t ab le 11 nmybus bit along with mybus bit decides which upstream channel is connected to the downstream channel. see t ab le 9 , t ab le 11 , and t ab le 12 . 0 mybus r/w see t ab le 11 mybus bit along with the nmybus bit decides which upstream channel is connected to the downstream channel. see t ab le 9 , t ab le 11 , and t ab le 12 .
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 12 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [1] mybus and nmybus is an exclusive-or type function where: equal values (00b or 11b) means that the master reading its control register has control of the bus. different values (01b or 10b) means that the master reading its control register does not have control of the bus. [1] buson and nbuson is an exclusive-or type function where: equal values (00b or 11b) means that the connection between the upstream and the downstream channels is off. different values (01b or 10b) means that the connection between the upstream and the downstream channels is on. switch to the new channel is done when the master initiating the switch request sends a stop command to the pca9541. if either master wants to change the connection of the downstream channel, it needs to write to its control register (reg#01), and then send a stop command because an update of the connection to the downstream according to the values in the two internal control registers happens only on a stop command. writing to one control register followed by a stop condition on the other master's channel will not cause an update to the downstream connection. when both masters request a switch to their own channel at the same time, the master who last wrote to its control register before the pca9541 receives a stop command wins the switching sequence. there is no arbitration performed. the auto increment feature (ai = 1) allows to program the pca9541 in 4 bytes: start 111a3a2a1a0 + 0 pca9541 address + write 00010000 select reg#00 with ai = 1 data reg#00 interrupt enable register data data reg#01 control register data stop table 9. mybus and nmybus truth table as a master reads its control register nmybus [1] mybus [1] slave channel 0 0 the master reading this combination has control of the bus. 1 0 the master reading this combination does not have control of the bus. 0 1 the master reading this combination does not have control of the bus. 1 1 the master reading this combination has control of the bus. table 10. buson and nbuson truth table nbuson [1] buson [1] slave channel 0 0 off 10on 01on 1 1 off
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 13 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset t ab le 12 describes which command needs to be written to the control register when a master device wants to take control of the i 2 c-bus. byte written to the control register is a function of the current i 2 c-bus control status performed after an initial reading of the control register. current status of the i 2 c-bus is determined by the bits mybus, nmybus, buson and nbuson is one of the following: ? the master reading its control register does not have control and the i 2 c-bus is off. ? the master reading its control register does not have control and the i 2 c-bus is on. ? the master reading its control register has control and the i 2 c-bus is off. ? the master reading its control register has control and the i 2 c-bus is on. i 2 c-bus off means that upstream and downstream channels are not connected together. i 2 c-bus on means that upstream and downstream channels are connected together. remark: only the 4 lsbs of the control register are described in t ab le 12 since only those bits control the i 2 c-bus control. the logic value for the 4 msbs is speci?c to the application and are not discussed in the table. the read sequence is performed by the master as: s - 111xxxx0 - 000x0001 - sr - 111xxxx1 - dataread - p the write sequence is performed by the master as: s - 111xxxx0 - 000x0001 - datawritten - p table 11. default control register values type version master bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nteston teston not used businit nbuson buson nmybus mybus pca9541/01 mst_0 0 0 0 0 0 1 0 0 mst_1 0 0 0 0 1 0 1 0 pca9541/03 mst_0 0 0 0 0 0 0 0 0 mst_1 0 0 0 0 0 0 1 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 14 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [1] only the 4 lsbs are shown. [2] x0x0 in binary = 0, 2, 8 or a in hexadecimal x0x1 in binary = 1, 3, 9 or b in hexadecimal x1x0 in binary = 4, 6, c or e in hexadecimal x1x1 in binary = 5, 7, d or f in hexadecimal [3] x can be either 0 or 1 since those bits are read-only bits. table 12. bus control sequence read control register performed by the master write control register performed by the master byte read [1] status nbuson buson nmybus mybus byte written [1] [2] action performed to take mastership nbuson [3] buson nmybus [3] mybus hex hex 0 bus off has control 0 0 0 0 4 bus on x 1 x 0 1 bus off no control 0 0 0 1 4 bus on, take control x 1 x 0 2 bus off no control 0 0 1 0 5 bus on, take control x 1 x 1 3 bus off has control 0 0 1 1 5 bus on x 1 x 1 4 bus on has control 0 1 0 0 - no change no write required 5 bus on no control 0 1 0 1 4 take control x 1 x 0 6 bus on no control 0 1 1 0 5 take control x 1 x 1 7 bus on has control 0 1 1 1 - no change no write required 8 bus on has control 1 0 0 0 - no change no write required 9 bus on no control 1 0 0 1 0 take control x 0 x 0 a bus on no control 1 0 1 0 1 take control x 0 x 1 b bus on has control 1 0 1 1 - no change no write required c bus off has control 1 1 0 0 0 bus on x 0 x 0 d bus off no control 1 1 0 1 0 bus on, take control x 0 x 0 e bus off no control 1 1 1 0 1 bus on, take control x 0 x 1 f bus off has control 1 1 1 1 1 bus on x 0 x 1
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 15 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 8.4 interrupt status registers the pca9541 provides 4 different types of interrupt: ? to indicate to the former i 2 c-bus master that it is not in control of the bus anymore ? to indicate to the new i 2 c-bus master that: C the bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). C a bus not well initialized condition has been detected by the pca9541 when the switch has been done (built-in bus recovery/initialization not active). this information can be used by the new master to initiate its own bus recovery/initialization sequence. ? indicate to both i 2 c-bus upstream masters that a downstream interrupt has been generated through the int_in pin. ? functionality wiring test. 8.4.1 bus control lost interrupt when an upstream master takes control of the i 2 c-bus while the other channel was using the downstream channel, an interrupt is generated to the master losing control of the bus ( int line goes low to let the master know that it lost the control of the bus) immediately after disconnection from the downstream channel. by setting the buslostmsk bit to 1, the interrupt is masked and the upstream master that lost the i 2 c-bus control does not receive an interrupt ( int line does not go low). 8.4.2 recovery/initialization interrupt before switching to a new upstream channel, an automatic bus recovery/initialization can be performed by the pca9541. this function is requested by setting the businit bit to 1. when the downstream bus has been initialized, an interrupt to the new master is generated ( int line goes low). by setting the businitmsk bit to 1, the interrupt is masked and the new master does not receive an interrupt ( int line does not go low). when the automatic bus recovery/initialization is not requested, if the built-in bus sensor function (sensing permanently the downstream i 2 c-bus traf?c) detects a non-idle condition (previous bus channel connected to the downstream slave channel, was between a start and stop condition), then an interrupt to the new master is sent ( int line goes low). this interrupt tells the new master that an external bus recovery/initialization must be performed. by setting the busokmsk bit to 1, the interrupt is masked and the new master does not receive an interrupt ( int line does not go low). remark: in this particular situation, after the switch to the new master is performed, a read of the interrupt status register is not possible if the switch happened in the middle of a read sequence because the new master does not have control of the sda line.
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 16 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 8.4.3 downstream interrupt an interrupt can also be generated by a downstream device by asserting the int_in pin low. when int_in is asserted low and if both intinmsk bits are not set to 1 by either master, int0 and int1 both go low. by setting the intinmsk bit to 1 by a master and/or the intinmsk bit to 1 by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt ( int0 and/or int1 line does (do) not go low). 8.4.4 functional test interrupt a master can send an interrupt to itself to test its own int wire or send an interrupt to the other master to test its int line. this is done by: ? setting the teston bit to 1 to test its own int line ? setting the nteston bit to 1 to test the other master int line setting the teston and/or nteston bits to 0 by a master will clear the interrupt(s). remark: interrupt outputs have an open-drain structure. interrupt input does not have any internal pull-up resistor and must not be left ?oating (that is, pulled high to v dd through resistor) in order to avoid any undesired interrupt conditions. 8.4.5 register 2: interrupt status register (b1:b0 = 10b) the interrupt status register for both the masters is identical and is described below. nevertheless, there are physically 2 internal interrupt registers, one for each upstream channel. when master 0 reads this register, the internal interrupt register 0 will be accessed. when master 1 reads this register, the internal interrupt register 1 will be accessed. table 13. register 2 - interrupt status register (b1:b0 = 10b) bit allocation 7 6 5 4 3 2 1 0 nmytest mytest 0 0 buslost busok businit intin table 14. register 2 - interrupt status (istat) register bit description legend: * default value bit symbol access value [1] description 7 nmytest [2] r only 0* no interrupt generated due to nteston bit from the other master (nteston = 0 from the other master) [3] 1 interrupt generated due to teston bit from the other master (nteston = 1 from the other master) [3] 6 mytest [2] r only 0* no interrupt generated by teston bit (teston = 0) [3] 1 interrupt generated by teston bit (teston = 1) [3] 5 - r only 0* not used 4 - r only 0* not used 3 buslost [4] r only 0* no interrupt generated to the previous master when switching to the new one is initiated 1 interrupt generated to the previous master when switching to the new one is initiated
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 17 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [1] default values are the same for pca9541/01 and pca9541/03. [2] reading the interrupt status register does not clear the mytest, nmytest or the intin bits. they are cleared if: int_in lines goes high for intin bit teston bit is cleared for mytest bit nteston bit is cleared for nmytest bit [3] interrupt on a master is cleared after teston bit is cleared by the same master or nteston bit is cleared by the other maste r. [4] businit, busok and buslost bits in the interrupt status register get cleared after a read of the same register is done. precisely, the register gets cleared on the second clock pulse during the read operation. [5] if the interrupt condition remains on int_in after the read sequence, another interrupt will be generated (if the interrupt has not been masked). 8.5 power-on reset when power is applied to v dd , an internal power-on reset holds the pca9541 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the internal registers are initialized to their default states, with: ? pca9541/01: default channel 0 (no stop detect) after power-up and/or insertion of the device in the main i 2 c-bus, the upstream channel 0 and the downstream slave channel are connected together. ? pca9541/03: default no channel (no stop detect) after power-up and/or insertion of the device in the main i 2 c-bus, no channel will be connected to the downstream channel. the device is ready to receive a start condition and its address by a master. if either register writes to its control register, then the connection between the upstream and the downstream channels is determined by the values on the control registers. thereafter, v dd must be lowered below 0.2 v to reset the device. 2 busok [4] r only 0* no interrupt generated by bus sensor function 1 interrupt generated by bus sensor function (masked when bus recovery/initialization requested) - bus was not idle when the switch occurred 1 businit [4] r only 0* no interrupt generated by the bus recovery/initialization function 1 interrupt generated by the bus recovery/initialization function; recovery/initialization done 0 intin [2] r only 0* no interrupt on interrupt input ( int_in) [5] 1 interrupt on interrupt input ( int_in) [5] table 14. register 2 - interrupt status (istat) register bit description continued legend: * default value bit symbol access value [1] description
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 18 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 8.6 external reset a reset can be accomplished by holding the reset pin low for a minimum of t w(rst)l . the pca9541 registers and i 2 c-bus state machine will be held in their default states until the reset input is once again high. this input typically requires a pull-up resistor to v dd . default states are: ? i 2 c-bus upstream channel 0 connected to the i 2 c-bus downstream channel for the pca9541/01 ? no i 2 c-bus upstream channel connected to the i 2 c-bus downstream channel for the pca9541/03. 8.7 voltage translation the pass gate transistors of the pca9541 are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data speci?ed in section 12 static char acter istics of this data sheet). in order for the pca9541 to act as a voltage translator, the v o(sw) voltage should be equal to, or lower than the lowest bus voltage. for example, if the main buses were running at 5 v, and the downstream bus was 3.3 v, then v o(sw) should be equal to or below 3.3 v to effectively clamp the downstream bus voltages. looking at figure 8 , we see that v o(sw)(max) will be at 3.3 v when the pca9541 supply voltage is 3.5 v or lower so the pca9541 supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 17 ). more information on voltage translation can be found in application note an262: pca954x family of i 2 c/smbus multiplexers and switches . (1) maximum (2) typical (3) minimum fig 8. pass gate voltage as a function of supply voltage v dd (v) 2.0 5.5 4.5 3.0 4.0 002aaa964 3.0 2.0 4.0 5.0 v o(sw) (v) 1.0 3.5 5.0 2.5 (1) (2) (3)
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 19 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 9. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 9 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 10 ). fig 9. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 10. de?nition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 20 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 9.3 system con?guration a device generating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 11 ). 9.4 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 11. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 12. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 21 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 9.5 bus transactions remark: if a third data byte is sent, it will not be acknowledged by the pca9541. remark: if a fourth data byte is read, the ?rst register will be accessed. fig 13. write to the interrupt enable and control registers using the auto-increment (ai) bit 002aab607 1 1 1 a3 a2 a1 a0 0 slave address r/w s start condition a acknowledge from slave 00010000 command code register auto increment a acknowledge from slave a p stop condition a acknowledge from slave acknowledge from slave data interrupt enable (ie) register data control register (control) (1) xx = 00: interrupt enable register xx = 01: control register xx = 10: int register (2) xx = 00: control register xx = 01: int register xx = 10: interrupt enable register (3) xx = 00: int register xx = 01: interrupt enable register xx = 10: control register fig 14. read the 3 registers using the auto-increment (ai) bit 002aab608 1 1 1 a3 a2 a1 a0 0 slave address r/w s start condition a acknowledge from slave 000100xx command code register access to register xx = 00, 01, or 10 auto increment a acknowledge from slave a p stop condition a no acknowledge from master acknowledge from master (1) (2) sr re-start condition 1 1 1 a3 a2 a1 a0 1 slave address r/w a acknowledge from slave a acknowledge from master (3)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 22 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset (1) we assume that a read of the control register was done by master 0 before this sequence and that 000x 0101 was read (master 1 c ontrolling the bus). fig 15. write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization requested) 002aab609 1 1 1 a3 a2 a1 a0 0 slave address r/w s start condition a acknowledge from slave 000ai0001 command code register auto increment a acknowledge from slave p stop condition a acknowledge from slave data control register sda_mst0 (1) 0 0 0 1 0 1 0 0 businit buson mybus after the stop condition master 1 is disconnected from the downstream channel. scl_mst0 if the interrupt is not masked (buslostmsk = 0) int1 123456789 scl_slave sda_slave a stop command int0 if the interrupt is not masked (businitmsk = 0) pca9541 has control of the bus master 0 has control of the bus master 1 has control of the bus master 0 must wait for the 'bus free time' value (between stop and start) defined in the i 2 c-bus specification before sending commands to the downstream devices.
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 23 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset (1) we assume that a read of the control register was done by master 0 before this sequence and that 000x 0101 was read (master 1 controlling the bus). fig 16. write to the control register and switch from channel 1 to channel 0 (bus recovery/initialization not requested) 002aab610 1 1 1 a3 a2 a1 a0 0 slave address r/w s start condition a acknowledge from slave 000ai0001 command code register auto increment a acknowledge from slave p stop condition a data control register sda_mst0 (1) 0 0 0 0 0 1 0 0 after the stop condition master 1 is disconnected from the downstream channel, and master 0 is connected to the downstream channel. scl_mst0 if the interrupt is not masked (buslostmsk = 0) int1 int0 if master 1 was not idle at the switching moment and the interrupt is not masked (businitmsk = 0) master 0 has control of the bus master 1 has control of the bus master 0 must wait for the 'bus free time' value (between stop and start) defined in the i 2 c-bus specification before sending commands to the downstream devices. acknowledge from slave businit buson mybus
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 24 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 10. application design-in information 10.1 speci?c applications the pca9541 is a 2-to-1 i 2 c-bus master selector designed for dual master, high reliability i 2 c-bus applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. the pca9541 can also be used in other applications, such as where masters share the same resource but cannot share the same bus, as a gatekeeper multiplexer in long single bus applications or as a bus initialization/recovery device. fig 17. typical application pca9541 scl_mst0 sda_mst0 int0 3.3 v master 0 002aab611 scl0 sda0 int0 int_in a3 a2 a1 v dd a0 v ss v dd reset0 v ss slave 1 sda scl slave 2 sda scl int slave 3 sda scl sda_slave scl_slave scl_mst1 sda_mst1 int1 3.3 v master 1 scl1 sda1 int1 v dd reset1 v ss reset slave card
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 25 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 10.2 high reliability systems in a typical multipoint application, shown in figure 18 , the two masters (for example, primary and back-up) are located on separate i 2 c-buses that connect to multiple downstream i 2 c-bus slave cards/devices via a pca9541/01 for non-hot swap applications to provide high reliability of the i 2 c-bus. i 2 c-bus commands are sent via the primary or back-up master and either master can take command of the i 2 c-bus. either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. the failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. for even higher reliability in multipoint backplane applications, two dedicated masters can be used for every card as shown in figure 19 . fig 18. high reliability backplane application fig 19. very high reliability backplane application 002aab612 master 1 scl1 sda1 master 0 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 pca9541 scl0 sda0 002aab613 scl1 sda1 master 0 pca9541 scl0 sda0 master 0 master 0 master 0 scl0 sda0 scl0 sda0 scl0 sda0 master 1 master 1 master 1 master 1 scl1 sda1 scl1 sda1 scl1 sda1 pca9541 pca9541 pca9541
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 26 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 10.3 masters with shared resources some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. the pca9541 can be used to separate the masters, as shown in figure 20 , but still allow shared access to slave devices, such as field replaceable unit (fru) eeproms or temperature sensors. 10.4 gatekeeper multiplexer the pca9541/03 can act as a gatekeeper multiplexer in applications where there are multiple i 2 c-bus devices with the same ?xed address (for example, eeproms with address of z as shown in figure 21 ) connected in a multipoint arrangement to the same i 2 c-bus. up to 16 hot swappable cards/devices can be multiplexed to the same bus master by using one pca9541/03 per card/device. since each pca9541/03 has its own unique address (for example, a, b, c, and so on), the eeproms can be connected to the master, one at a time, by connecting one pca9541/03 (master 0 position) while keeping the rest of the cards/devices isolated (off position). the alternative, shown with dashed lines, is to use a pca9548 1-to-8 channel switch on the master card and run 8 i 2 c-bus devices, one to each eeprom card, to multiplex the master to each card. the number of card pins used is the same in either case, but there are 7 less pairs of sda/scl traces on the printed-circuit board if the pca9541/03 is used. fig 20. masters with shared resources application 002aab614 pca9541 slave a0 slave a1 slave a2 master a pca9541 slave b0 slave b1 slave b2 master b assembly a assembly b sda/scl sda/scl main master
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 27 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 10.5 bus initialization/recovery to initialize slaves without hardware reset if the i 2 c-bus is hung, i 2 c-bus devices without a hardware reset pin (for example, slave 1 and slave 2 in figure 22 ) can be isolated from the master by the pca9541/03. the pca9541/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (for example, slave 0). the bus master can then command the pca9541/03 to send 9 clock pulses/stop condition to reset the downstream i 2 c-bus devices before they are reconnected to the master or leave the downstream devices isolated. fig 21. gatekeeper multiplexer application 002aab615 master 0 pca9541 pca9548 eeprom z a pca9541 eeprom z b pca9541 eeprom z c pca9541 eeprom z d pca9541 eeprom z e pca9541 eeprom z f pca9541 eeprom z g pca9541 eeprom z h fig 22. bus initialization/recovery application 002aab616 pca9541/03 slave 1 sda scl slave 2 slave i 2 c-bus master slave 0 reset sda/scl
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 28 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 11. limiting values [1] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not exceed 125 c. 12. static characteristics table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss (ground = 0 v). [1] symbol parameter conditions min max unit v dd supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i i input current - 20 +20 ma i o output current - 25 +25 ma i dd supply current - 100 +100 ma i ss ground supply current - 100 +100 ma p tot total power dissipation - 400 mw t stg storage temperature - 60 +150 c t amb ambient temperature operating in free air - 40 +85 c table 16. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 5.5 v i dd supply current operating mode; no load; v i =v dd or v ss ; f scl = 100 khz v dd = 3.6 v - 152 200 m a v dd = 5.5 v - 349 600 m a i stb standby current standby mode; no load; v i =v dd or v ss ; f scl = 0 khz v dd = 3.6 v - 30 80 m a v dd = 5.5 v - 40 100 m a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.5 2.1 v input scl_mstn; input/output sda_mstn (upstream and downstream channels) v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss v dd = 2.3 v to 3.6 v - 4 5 pf v dd = 3.6 v to 5.5 v - 4 6 pf
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 29 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [1] v dd must be lowered to 0.2 v in order to reset part. select inputs a0 to a3, int_in, reset v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i li input leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss v dd = 2.3 v to 3.6 v - 2 3 pf v dd = 3.6 v to 5.5 v - 2 5 pf pass gate r on on-state resistance v dd = 4.5 v to 5.5 v; v o = 0.4 v; i o =15ma 41224 w v dd = 3.0 v to 3.6 v; v o = 0.4 v; i o =15ma 51430 w v dd = 2.3 v to 2.7 v; v o = 0.4 v; i o =10ma 71755 w v o(sw) switch output voltage v i(sw) =v dd = 5.0 v; i o(sw) = - 100 m a - 3.6 - v v i(sw) =v dd = 4.5 v to 5.5 v; i o(sw) = - 100 m a 2.6 - 4.5 v v i(sw) =v dd = 3.3 v; i o(sw) = - 100 m a - 2.2 - v v i(sw) =v dd = 3.0 v to 3.6 v; i o(sw) = - 100 m a 1.6 - 2.8 v v i(sw) =v dd = 2.5 v; i o(sw) = - 100 m a - 1.5 - v v i(sw) =v dd = 2.3 v to 2.7 v; i o(sw) = - 100 m a 1.1 - 2.0 v i l leakage current v i =v dd or v ss - 1- +1 m a int0 and int1 outputs i ol low-level output current v ol = 0.4 v 3 - - ma table 16. static characteristics continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 30 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 13. dynamic characteristics [1] pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. [2] after this period, the ?rst clock pulse is generated. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the unde?ned region of the falling edge of scl. table 17. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay (sda_mstn to sda_slave) or (scl_mstn to scl_slave) [1] - 0.3 - 0.3 ns f scl scl clock frequency 0 100 0 400 khz f scl(init/rec) scl clock frequency (bus initialization/bus recovery) 50 150 50 150 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition [2] 4.0 - 0.6 - m s t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 [3] 3.45 0 [3] 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [4] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [4] 300 ns c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes that must be suppressed by the input ?lter - 50 - 50 ns t vd;dat data valid time high-to-low [5] -1 - 1 m s low-to-high [5] - 0.6 - 0.6 m s t vd;ack data valid acknowledge time - 1 - 1 m s int t v(int_in-intn) valid time from pin int_in to pin intn signal -4 - 4 m s t d(int_in-intn) delay time from pin int_in to pin intn inactive -2 - 2 m s t w(rej)l low-level rejection time int_in input 1 - 1 - m s t w(rej)h high-level rejection time int_in input 0.5 - 0.5 - m s reset t w(rst)l low-level reset time 4 - 4 - ns t rst reset time sda clear 500 - 500 - ns t rec;sta recovery time to start condition [6] [7] 0- 0 -ns
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 31 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset [4] c b = total capacitance of one bus line in pf. [5] measurements taken with 1 k w pull-up resistor and 50 pf load. [6] resetting the device while actively communicating on the bus may cause glitches or errant stop conditions. [7] upon reset, the full delay will be the sum of t rst and the rc time constant of the sda bus. fig 23. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times, refer to v il and v ih . fig 24. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab175 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 32 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 14. test information fig 25. de?nition of reset timing sda scl 002aae735 t rst 50 % 30 % 50 % 50 % 50 % t rec;sta t w(rst)l reset intn start t rst ack or read cycle de?nitions test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 26. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aab393 r t v i v dd dut 6.0 v open v ss
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 33 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 15. package outline fig 27. package outline sot109-1 (so16) x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 34 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset fig 28. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 35 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset fig 29. package outline sot629-1 (hvqfn16) terminal 1 index area 0.65 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.25 1.95 y 1 4.1 3.9 2.25 1.95 e 1 1.95 e 2 1.95 0.38 0.23 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot629-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot629-1 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 58 16 13 12 9 4 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 36 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 37 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 16.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 30 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 18 and 19 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 30 . table 18. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 19. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 38 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 17. abbreviations msl: moisture sensitivity level fig 30. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 20. abbreviations acronym description ai auto increment cdm charged device model dut device under test eeprom electrically erasable programmable read-only memory esd electrostatic discharge fru field replaceable unit hbm human body model i 2 c-bus inter integrated circuit bus ic integrated circuit mm machine model por power-on reset rc resistor-capacitor network smbus system management bus
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 39 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 18. revision history table 21. revision history document id release date data sheet status change notice supersedes pca9541_7 20090702 product data sheet - pca9541_6 modi?cations: ? type numbers pca9541d//02, pca9541pw/02 and pca9541bs/02 are withdrawn; this affects: C section 1 gener al descr iption , 2 nd paragraph modi?ed; (old) 11 th paragraph deleted C section 2 f eatures , (old) 4 th bullet item deleted C t ab le 1 order ing inf or mation modi?ed C t ab le 2 mar king codes modi?ed C figure 2 , figure 3 and figure 4 modi?ed C t ab le 6 register 0 - interr upt enab le (ie) register bit descr iption , t ab le note [1] modi?ed C t ab le 8 register 1 - control register (b1:b0 = 01b) bit descr iption , t ab le note [1] modi?ed C t ab le 11 def ault control register v alues modi?ed C t ab le 14 register 2 - interr upt status (ist a t) register bit descr iption , t ab le note [1] modi?ed C section 8.5 p o w er-on reset , (old) 2 nd bullet item deleted C section 8.6 exter nal reset , (old) 2 nd bullet item deleted C section 10.2 high reliability systems , 1 st paragraph modi?ed ? (old) table 16 static characteristics (2.3 v to 3.6 v) and (old) table 17 static characteristics (3.6 v to 5.5 v) are merged. ? t ab le 16 static char acter istics , sub-section supply: C i stb (typ) at condition v dd = 2.3 v to 3.6 v changed from 10 m a to 30 m a C i stb (max) at condition v dd = 2.3 v to 3.6 v changed from 100 m a to 80 m a C i stb (typ) at condition v dd = 3.6 v to 5.5 v changed from 10 m a to 40 m a C i stb (max) at condition v dd = 3.6 v to 5.5 v changed from 200 m a to 100 m a ? t ab le 16 static char acter istics , sub-section input scl_mstn; input/output sda_mstn (upstream and downstream channels): C for condition v dd = 3.6 v to 5.5 v, deleted i il and i ih speci?cations (was in old table 17) ? t ab le 16 static char acter istics , sub-section select inputs a0 to a3, int_in, reset: C for condition v dd = 3.6 v to 5.5 v, i li (max) changed from +50 m a to +1 m a (from old table 17) ? t ab le 16 static char acter istics , sub-section pass gate: C for condition v dd = 3.6 v to 5.5 v, i l (max) changed from +100 m a to +1 m a (was in old table 17) ? figure 25 de? nition of reset timing modi?ed: C changed signal name from ledx to intn C deleted led off pca9541_6 20080911 product data sheet - pca9541_5 pca9541_5 20071001 product data sheet - pca9541_4 pca9541_4 20060104 product data sheet - pca9541_3 pca9541_3 (9397 750 14746) 20050713 product data sheet - pca9541_2 pca9541_2 (9397 750 13629) 20041001 product data sheet - pca9541_1 pca9541_1 (9397 750 12453) 20031202 product data sheet 853-2436 01-a14594 -
pca9541_7 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 07 2 july 2009 40 of 41 nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 19.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 19.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 19.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9541 2-to-1 i 2 c-bus master selector with interrupt logic and reset ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 2 july 2009 document identifier: pca9541_7 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 7 8.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 command code . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3 interrupt enable and control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.3.1 register 0: interrupt enable (ie) register (b1:b0 = 00b) . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3.2 register 1: control register (b1:b0 = 01b) . . 11 8.4 interrupt status registers . . . . . . . . . . . . . . . . 15 8.4.1 bus control lost interrupt . . . . . . . . . . . . . . . . . 15 8.4.2 recovery/initialization interrupt. . . . . . . . . . . . 15 8.4.3 downstream interrupt . . . . . . . . . . . . . . . . . . . 16 8.4.4 functional test interrupt . . . . . . . . . . . . . . . . . 16 8.4.5 register 2: interrupt status register (b1:b0 = 10b) . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 external reset . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.7 voltage translation . . . . . . . . . . . . . . . . . . . . . 18 9 characteristics of the i 2 c-bus. . . . . . . . . . . . . 19 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 start and stop conditions . . . . . . . . . . . . . 19 9.3 system con?guration . . . . . . . . . . . . . . . . . . . 20 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.5 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 21 10 application design-in information . . . . . . . . . 24 10.1 speci?c applications . . . . . . . . . . . . . . . . . . . . 24 10.2 high reliability systems . . . . . . . . . . . . . . . . . . 25 10.3 masters with shared resources. . . . . . . . . . . . 26 10.4 gatekeeper multiplexer . . . . . . . . . . . . . . . . . . 26 10.5 bus initialization/recovery to initialize slaves without hardware reset . . . . . . . . . . . . 27 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 12 static characteristics. . . . . . . . . . . . . . . . . . . . 28 13 dynamic characteristics . . . . . . . . . . . . . . . . . 30 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 32 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 16 soldering of smd packages . . . . . . . . . . . . . . 36 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 36 16.2 wave and re?ow soldering . . . . . . . . . . . . . . . 36 16.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 36 16.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 37 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 39 19 legal information . . . . . . . . . . . . . . . . . . . . . . 40 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 19.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20 contact information . . . . . . . . . . . . . . . . . . . . 40 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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